74LS670 4-By-4 Register Files With 3-State Outputs IC (74670 IC) DIP-16 Package

The functional characteristics of the 74F194 4-Bit Bidirectional Shift Register are indicated in the Logic Diagram and Function Table. The register is fully synchronous, with all operations taking place in less than 9ns (typical) for 74F, making the device especially useful for implementing very high speed CPUs, or for memory buffer registers. The 74F194 design has special logic features which increase the range of application. The synchronous operation of the device is determined by two Mode Select inputs, S0 and S1. As shown in the Mode Select-Function Table, data can be entered and shifted from left to right (shift right, Q0→Q1, etc.), or right to left (shift left,Q3→Q2, etc.), or parallel data  can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are Low, existing data is retained in a hold (do nothing) mode. The first and last stages provide D-type Serial Data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode Select and data inputs on the74F194 are edge-triggered, responding only to the Low-to-High transition of the Clock (CP). Therefore, the only timing restriction is that the Mode Select and selected data inputs must be stable one setup time prior to the Low-to-High transition of the clock pulse. Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data(DSR, DSL) can change when the clock is in either state, provide donly the recommended setup and hold times, with respect to the clock rising edge, are observed. The four Parallel Data inputs(D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs whenS0 and S1 are High is transferred to the Q0–Q3 outputs respectively, following the next Low-to-High transition of the clock. When Low, the asynchronous Master Reset (MR) overrides all other input conditions and forces the Q outputs Low

Features :-

• Shift right and shift left capability
• Synchronous parallel and serial data transfer
• Easily expanded for both serial and parallel operation
• Asynchronous Master Reset
• Hold (do nothing) mode

The 74F541 except that the inputs and outputs are on opposite sides of the package (see Connection Diagrams). This pinout arrangement makes these devices especially useful as output ports for microprocessors, allowing ease of layout and greater PC board density

Features :-

• 3-STATE outputs drive bus lines
• Inputs and outputs opposite side of package, allowing easier interface to microprocessors

This device contains gates configured to perform a 4-2-3-2input AND-OR-INVERT function.

74HC158 is a 16 Pin Quad 2-Input Multiplexer IC having 2V to 6V Operating Voltage range with 1uA Low Input current and high noise immunity. It select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions.

Features:-

• Common Select Input
• Separate Enable Inputs
• Buffered inputs and Outputs
• Fanout (Over Temperature Range)
• Standard Outputs  : 10 LSTTL Loads
• Bus Driver Outputs : 15 LSTTL Loads
• Wide Operating Temperature Range : -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
• 2V to 6V Operation
• High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V
• HCT Types-
• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il≤1μA at VOL, VOH