74F138 1-of-8 Decoder/Demultiplexer IC (74138) DIP-16 Package

The functional characteristics of the 74F194 4-Bit Bidirectional Shift Register are indicated in the Logic Diagram and Function Table. The register is fully synchronous, with all operations taking place in less than 9ns (typical) for 74F, making the device especially useful for implementing very high speed CPUs, or for memory buffer registers. The 74F194 design has special logic features which increase the range of application. The synchronous operation of the device is determined by two Mode Select inputs, S0 and S1. As shown in the Mode Select-Function Table, data can be entered and shifted from left to right (shift right, Q0→Q1, etc.), or right to left (shift left,Q3→Q2, etc.), or parallel data  can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are Low, existing data is retained in a hold (do nothing) mode. The first and last stages provide D-type Serial Data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode Select and data inputs on the74F194 are edge-triggered, responding only to the Low-to-High transition of the Clock (CP). Therefore, the only timing restriction is that the Mode Select and selected data inputs must be stable one setup time prior to the Low-to-High transition of the clock pulse. Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data(DSR, DSL) can change when the clock is in either state, provide donly the recommended setup and hold times, with respect to the clock rising edge, are observed. The four Parallel Data inputs(D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs whenS0 and S1 are High is transferred to the Q0–Q3 outputs respectively, following the next Low-to-High transition of the clock. When Low, the asynchronous Master Reset (MR) overrides all other input conditions and forces the Q outputs Low

Features :-

• Shift right and shift left capability
• Synchronous parallel and serial data transfer
• Easily expanded for both serial and parallel operation
• Asynchronous Master Reset
• Hold (do nothing) mode

The 74F393 is a Dual Ripple Counter with separate Clock (CPn) and Master Reset (MR) inputs to each counter. The two counters are identified by the “a” and “b” suffixes in the pin configuration. The operation of each half of the 74F393 is the same. The counters are triggered by a High-to-Low transition of the Clock (CPa and CPb)inputs. The counter outputs are internally connected to provide Clock inputs to succeeding stages. The outputs of the ripple counter do not change synchronously and should not be used for high speed address decoding. The Master Resets (MRa and MRb) are active High asynchronous inputs; one for each 4-bit counter. A High level in the MR input overrides the Clock and sets the outputs Low

Features :-

• Two 4-bit binary counters
• Two Master Resets to clear each 4-bit counter individually

The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC

Features :-

• Complies with JEDEC standard no. 7A
• Input levels:

For 74HC163: CMOS level For 74HCT163: TTL level

• Synchronous counting and loading
• 2 count enable inputs for n-bit cascading
• Synchronous reset
• Positive-edge triggered clock
• ESD protection:

HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V

• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

The 74HC20 is a 14 Pin Quad 4-Input NAND Gate IC. This device contains four independent gates each of which performs the logic NAND function. NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.