74F393 Dual 4-Bit Binary Ripple Counter IC (74393) DIP-14 Package

The 74HC161 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters maybe preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time ,according to the following formula:

74HC109 Dual J-K Positive-Edge-Triggered Flip-Flop IC – DIP-16 Package The 74HC109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product is known as 74109 IC, 74109 SMD IC, 74HC109 IC, 74HC109 SMD IC, Components, Dual J-K Positive-Edge-Triggered Flip-Flops IC, Dual J-K Positive-Edge-Triggered Flip-Flops SMD IC, SN74HC109D, CD74HC109M, 74HC109D, CD74HC109E, SN74HC109N, CD74HC109ME4.

Features :-

• Input Levels :

– For 74HC109: CMOS level – For 74HCT109: TTL level

• J and K inputs for easy D-type flip-flop
• Toggle flip-flop or “do nothing” mode
• Specified in compliance with JEDEC standard no. 7A
• ESD protection:

– HBM JESD22-A114F exceeds 2000 V – MM JESD22-A115-A exceeds 200 V

• Multiple package options

The 74F138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active low outputs (Q0 – Q7). The device features three enable inputs; two active low (E0, E1) and one active high (E2). Every output will be high unless E0 and E1 are low and E2 is high. This multiple enable function allows easy parallel expansion of the device to 1–of–32 (5 lines to 32 lines) decoder with just four 74F138s and one inverter The device can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Enable inputs not used must be permanently tied to their appropriate active high or active low state.

Features :-

• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Industrial temperature range available (–40°C to +85°C)

 

The 74F640 is an octal transceiver featuring inverting 3-State bus compatible outputs in both transmit and receive directions. The B port outputs are capable of sinking 64mA and sourcing 15mA, providing very good capacitive drive characteristics. The device features an Output Enable (OE) input for easy cascading and Transmit/Receiver (T/R) input for direction control. The 3-State outputs, B0–B7, have been designed to prevent output bus loading if the power is removed from the device

Features :-

• High-impedance NPN base inputs for reduced loading (70µA in High and Low states)
• Ideal for applications which require high-output drive and minimal bus loading
• Inverting version of 74F245
• Octal bidirectional bus interface
• 3-State outputs sink 64mA and source 15mA