74F280 9-Bit Parity Generator/Checker IC (74280) DIP-14 Package

The 74F251 is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided

Features :-

• Multifunctional Capacity
• On-Chip Select Logic Decoding
• Inverting and Noninverting 3-State Output

The 74HC194/74HCT194 is a 4-bit bidirectional universal shift register. The synchronous operation of the device is determined by the mode select inputs (S0, S1). In parallel load mode (S0 and S1 HIGH) data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs. When S0 is HIGH and S1 is LOW data is entered serially via DSL and shifted from left to right; when S0 is LOW and S1 is HIGH data is entered serially via DSR and shifted from right to left. DSR and DSL allow multistage shift right or shift left data transfers without interfering with parallel load operation. If both S0 and S1 are LOW, existing data is retained in a hold mode. Mode select and data inputs are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. When LOW, the asynchronous master reset (MR) overrides all other input conditions and forces the Q outputs LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74F640 is an octal transceiver featuring inverting 3-State bus compatible outputs in both transmit and receive directions. The B port outputs are capable of sinking 64mA and sourcing 15mA, providing very good capacitive drive characteristics. The device features an Output Enable (OE) input for easy cascading and Transmit/Receiver (T/R) input for direction control. The 3-State outputs, B0–B7, have been designed to prevent output bus loading if the power is removed from the device

Features :-

• High-impedance NPN base inputs for reduced loading (70µA in High and Low states)
• Ideal for applications which require high-output drive and minimal bus loading
• Inverting version of 74F245
• Octal bidirectional bus interface
• 3-State outputs sink 64mA and source 15mA

This device contains gates configured to perform a 4-2-3-2input AND-OR-INVERT function.