74F521 8-Bit Identity Comparator IC (74521) DIP-20 Package

In Stock

Category: 74 Series IC

The 74F521 is an expandable 8-bit comparator. It compares two words of up to eight bits each and provides a LOW output when the two words match bit for bit. The expansion input IA=B also serves as an active LOW enable input

Features :-

Compares two 8-bit words in 6.5 ns typ
Expandable to any word length
20-pin package

Description
Reviews (0)

Description

Specifications :-

Supply voltage : +4.5V – +5.5V
High-level input voltage : 2.0V
Low-level input voltage : 0.8V
Input Clamp Diode Voltage : -1.2V
Input High Current : 5.0µA
Input High Current Breakdown Test : 7.0µA
Output High Leakage Current : 50µA
Output Short-Circuit Current : -60 -150mA
Power Supply Current : 32mA

Package Includes :-

1 X 74F521 8-Bit Identity Comparator IC (74521) DIP-20 Package

Reviews

There are no reviews yet.

Be the first to review “74F521 8-Bit Identity Comparator IC (74521) DIP-20 Package”

Related products

Add to wishlist Compare

74HC163 Presettable synchronous Binary counter IC (74163) DIP-16 Package

The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal look-head carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC

Features :-

Complies with JEDEC standard no. 7A
Input levels:

For 74HC163: CMOS level For 74HCT163: TTL level

Synchronous counting and loading
2 count enable inputs for n-bit cascading
Synchronous reset
Positive-edge triggered clock
ESD protection:

HBM JESD22-A114F exceeds 2 000 V MM JESD22-A115-A exceeds 200 V

Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

ENQUIRY!

Add to wishlist Compare

74F251 8-Inputs Multiplexer with 3-State Outputs IC (74251) DIP-16 Package

ENQUIRY!

Add to wishlist Compare

74HC241 8-Bit Buffer Line Driver IC (74241 IC) DIP-20 Package

The 74HC241; 74HCT241 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on 1OE or LOW on 2OE causes the associated outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. The 74HCT241 device features reduced input threshold levels to allow interfacing to TTL logic levels.

ENQUIRY!

Add to wishlist Compare

74HC237 3-to-8 line Decoder/Demultiplexer IC (74237 IC) DIP-16 Package

The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems.

ENQUIRY!

Add to wishlist Compare

74HC109 Dual J-K Negative-Edge-Triggered Flip-Flops IC (74109) DIP-16 Package

74HC109 Dual J-K Positive-Edge-Triggered Flip-Flop IC – DIP-16 Package The 74HC109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product is known as 74109 IC, 74109 SMD IC, 74HC109 IC, 74HC109 SMD IC, Components, Dual J-K Positive-Edge-Triggered Flip-Flops IC, Dual J-K Positive-Edge-Triggered Flip-Flops SMD IC, SN74HC109D, CD74HC109M, 74HC109D, CD74HC109E, SN74HC109N, CD74HC109ME4.