The 74HC423 is a dual retriggerable monostable multivibrator with output pulse width control by two methods. The basic pulse time is programmed by selection of an external resistor (REXT) and capacitor (CEXT). Once triggered, the basic output pulse width may be extended by retriggering (nA) or (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. When nRD is LOW, it forces the nQ output LOW, the nQ output HIGH and also inhibits the triggering. Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower input rise and fall times. The '423' is identical to the '123' but cannot be triggered via the reset input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74HC4049 is a high-speed Si-gate CMOS device and is pin compatible with the “4049” of the “4000B” series. It is specified in compliance with JEDEC standard no. 7A.The 74HC4049 provides six inverting buffers with a modified input protection structure, which has no diode connected to VCC. Input voltages of up to 15 V may therefore be used. This feature enables the inverting buffers to be used as logic level translators, which will convert high level logic to low level logic, while operating from a low voltage power supply. For example 15 V logic (“4000B series”) can be converted down to 2 V logic. The actual input switch level remains related to the VCC and is the same as mentioned in the family characteristics .At the same time each part can be used as a simple inverter without level translation

The 74HC40103 is a high-speed Si-gate CMOS device and are pin compatible with the 40103 of the 4000B series. The 74HC40103 is specified in compliance with JEDEC standard no. 7A. The 74HC40103 consists of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The 74HC40103 contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic .In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. The 74HC40103 may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode

The 74HC292/7292 and HC294/7294 are high speed CMOS PROGRAMMABLE DIVIDER/TIMER fabricated with silicon C2 MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. These devices are programmable frequency dividers. The type shave two clock inputs, either one may be used for clock gating. (see the function table). The HC292/7292 can divide from 22 to 231, and the HC294/7294 can divide from 22 to 215. The types feature an active-low clear input to initialize the state of all flip-flops. To facilitate incoming inspection, test points are provided. (TP1, TP2 and TP3 on the HC292/7292 and TP on the HC294/7294). All inputs are equipped with protection circuits against static discharge and transient excess voltage. HC292/294 have Q output with ”Totem pole” configuration and test point TP with ”Open Drain” output configuration. HC7292/7294 have all outputs ”Totem Pole”.