74HC4016 Quad Analog Switch Multiplexer Demultiplexer IC (744016 IC) DIP-14 Package

The  F280  is  a  high-speed  parity  generator/checker  that accepts  nine  bits  of  input  data  and  detects  whether  an even or an odd number of these inputs is HIGH. If an even number of inputs is HIGH, the Sum Even output is HIGH. I fan odd number is HIGH, the Sum Even output is LOW. The Sum Odd output is the complement of the Sum Even out-put

The F74 is a dual D-type flip-flop with Direct Clear and Set inputs  and  complementary  (Q,  Q)  outputs.  Information  at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold  voltage  has  been  passed,  the  Data  input  is locked out and information present will not be transferred to the  outputs  until  the  next  rising  edge  of  the  Clock  Pulse input.

Features :-

• Asynchronous Inputs:
• LOW input to SD sets Q to HIGH level
• LOW input to CD sets Q to LOW level
• Clear and Set are independent of clock
• Simultaneous LOW on CD and SD makes both Q and Q HIGH

This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs. A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F574 is characterized for operation from 0°C to 70°C.

Features :-

• Eight D-Type Flip-Flops in a Single Package
• 3-State Bus-Driving True Outputs
• Full Parallel Access for Loading
• Buffered Control Inputs
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs

The 74F521 is an expandable 8-bit comparator. It compares two words of up to eight bits each and provides a LOW output when the two words match bit for bit. The expansion input IA=B also serves as an active LOW enable input

Features :-

• Compares two 8-bit words in 6.5 ns typ
• Expandable to any word length
• 20-pin package