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The 74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.
The 74LS170 is a high-speed, low-power 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. Open-collector outputs make it possible to connect up to 128 outputs in a wired-AND configuration to increase the word capacity up to 512 words. Any number of these devices can be operated in parallel to generate an n-bit length. The 74LS670 provides a similar function to this device but it features 3-state outputs
Applications:-
Random access register files are suitable for scratch-pad memories. This function is useful for communication between different controllers or processors or as a temporary fast storage.
The 74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
74LS161 4-Bit Binary Counter IC circuit designed as a synchronous reversible up-down counter. These synchronous, presettable counters provide an internal carry look-ahead feature for application in high-speed counting designs. The carry output decoded via a NOR gate. Thus preventing spikes during the normal counting mode of operation 74LS161 comes with a 4-bit binary counter in which Synchronous operation provided by all flip-flops clocked simultaneously. As a result, the outputs change simultaneously as instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) fringe of the clock input waveform.
This counter made fully programmable that the outputs also preset to either level by placing a low or high. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter. And causes the outputs to agree with the data inputs after the next clock pulse. This performed regardless of the levels of the enable input. The clock down up and load inputs buffered to lower the drive requirement. This significantly reduces the amount of clock drivers etc required for long parallel words.
he clear function for the 74LS161 is synchronous. And a low level at the clear input sets all four of the flip-flop outputs LOW, no matter the level of clock, load, or enable inputs. This synchronous clear allows the count length to modified easily, as decoding the maximum count desired often accomplished with one external NAND circuit. The gate output connected to the clear input to synchronously clear the counter to all or any low outputs.
The 74LS158 is a high speed Quad 2-input Multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the selected data in the inverted form. The LS158 can also generate any four of the 16 different functions of two variables. The LS158 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families
This data selector/multiplexer contains full on-chip decoding to select the desired data source. The 74LS151 selects one-of-eight data sources. The 74LS151 has a strobe input which must be at a low logic level to enable these devices. A high level at the strobe forces the W output HIGH, and the Y output LOW. The 74LS151 features complementary W and Y outputs.
74LS15 Triple 3-InputT AND Gate IC (7415 IC) DIP-14 Package
74LS15 designed as a high-speed three independent 3-input positive-AND gates IC fabricated in low power schotkey technology. The 74LS15 is a three-input positive-AND gate IC with three separate inputs built in low-power Schotkey technology. The logic AND function is performed by each of the three separate gates in this device. They use positive logic to perform the Boolean functions Y = A • B • C. This IC is designed to operate at temperatures ranging from 55°C to 125°C, which is the complete military temperature range. The 74LS15 is available in 14-pin PDIP wide-body surface-mount packages. The 74HC logic family is pin-out compatible with the 74LS logic family of high grade. It features a 4.5V to 5.5V supply voltage range. The 74LS15 IC uses advanced silicon-gate CMOS technology to achieve operating rates that are practically identical to LS-TTL gates while consuming less power than conventional CMOS integrated circuits. The 74LS15 has a strong noise immunity and, as a result, can drive TTL loads. Internal diode clamps to VCC and ground protect all inputs from static discharge damage. The AND gate designed as a basic digital logic gate that implements logical conjunction. An AND gate operates on logical multiplication rules. If all the inputs to the AND gate are HIGH, then the output will be high. If none or not all inputs to the AND gate are HIGH, results in LOW output.
Applications:-
- Combining power good signals
- Enable digital signals
These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The 74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The 74LS139 comprises two separate two-line-to-four line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications.
These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear.
Applications :-
- Its is commonly used in delay & timing circuits.
- It is also used for temporary memories.
74LS12 Triple 3-Input Positive NAND Gate IC (7412 IC) DIP-14 Package
The 74LS12 Triple 3-Input Positive NAND Gates With Collector Outputs contains three 3 input independent gates each of which performs the positive logic NAND function.74LS12 IC can be soldered directly to the circuit board or can be mounted on a 14 pin IC base. 74LS12 Triple 3-Input Positive NAND Gates With Collector Outputs circuit is designed such that the operation produced on the inputs of pin are (1&2&3&4 NAND 10&11&12&13) is produced on the pin 8 . Operating supply voltages to the IC can vary between 4.5V to 5V and to a maximum of 5.5V and the input logic levels to the device in ‘0’ (LOW) state is max. 0.7V and for ‘1’ (HIGH) state is min 2V.
This device contains six independent gates each of which performs the logic INVERT function. The open-collector outputs require external pull-up resistors for proper logical operation.
These devices contain four independent 2-input-NAND gates. The open-collector outputs require pull-up resistors to perform correctly. They may be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOH levels.
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable, one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC
The M74HC646 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, (3-STATE) fabricated in silicon gate C2 MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers on the low-to-high transition of the appropriate clock pin (Clock AB - or Clock BA). Enable(G) and direction (DIR) pins are provided to control the
transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored
in either register or in both. The select controls (Select AB select BA) can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode (enable G high), ”A” data may be stored in one register and/or ”B” data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. All inputs are equipped with protection circuits
The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
These 8-bit addressable latches are designed for general purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single line data in eight addressable latches, and being a 1-of-8 decoder or demultiplexer with active high outputs
Four distinct modes of operation are selectable by controlling the clear (CLR) and enable (G) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch will follow the data input with ail unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, enable G should be held high (inactive) while the address lines are changing.. In the 1-of-8 decoding or demultiplexing mode, the addressed output will follow the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs.
