74LS154 4-Line to 16-Line Decoder/Demultiplexer IC (74154 IC) DIP-24 Package

The 74F182 is a high-speed carry lookahead generator. It is  generally  used  with  the  74F181  or  74F381  4-bit  arithmetic  logic  units  to  provide  high-speed  lookahead  over word lengths of more than four bits

Features :-

• Provides lookahead carries across a group of four ALUs
• Multi-level  lookahead  high-speed  arithmetic  operation over long word lengths

This device contains gates configured to perform a 4-2-3-2input AND-OR-INVERT function.

The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems.

The 74F164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered through one of two inputs (Dsa, Dsb); either input can be used as an active High enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied High. Data shifts one place to the right on each Low-to-High transition of the clock (CP) input, and enters into Q0 the logical AND of the two data inputs (Dsa, Dsb) that existed one setup time before the rising edge. A Low level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs Low.

Features :-

• Gated serial data inputs
• Typical shift frequency of 100MHz
• Asynchronous Master Reset
• Buffered clock and data inputs
• Fully synchronous data transfer
• Industrial temperature range available (–40 to +85 °C)