74LS962 Dual Rank 8-Bit Tri-State Shift Register IC (74962 IC) DIP-16 Package

The  74F113  offers  individual  J,  K,  Set and  Clock inputs. When the clock goes  HIGH, the inputs are enabled  and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flip-flop  will  perform  according  to  the  Truth  Table  as  long  as minimum setup and hold times are observed. Input data is transferred  to  the  outputs  on  the  falling  edge  of  the  clock pulse.

Features :-

• Asynchronous input: LOW input to SD sets Q to HIGH level Set is independent of clock

The 74F138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active low outputs (Q0 – Q7). The device features three enable inputs; two active low (E0, E1) and one active high (E2). Every output will be high unless E0 and E1 are low and E2 is high. This multiple enable function allows easy parallel expansion of the device to 1–of–32 (5 lines to 32 lines) decoder with just four 74F138s and one inverter The device can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Enable inputs not used must be permanently tied to their appropriate active high or active low state.

Features :-

• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Industrial temperature range available (–40°C to +85°C)

 

The functional characteristics of the 74F194 4-Bit Bidirectional Shift Register are indicated in the Logic Diagram and Function Table. The register is fully synchronous, with all operations taking place in less than 9ns (typical) for 74F, making the device especially useful for implementing very high speed CPUs, or for memory buffer registers. The 74F194 design has special logic features which increase the range of application. The synchronous operation of the device is determined by two Mode Select inputs, S0 and S1. As shown in the Mode Select-Function Table, data can be entered and shifted from left to right (shift right, Q0→Q1, etc.), or right to left (shift left,Q3→Q2, etc.), or parallel data  can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are Low, existing data is retained in a hold (do nothing) mode. The first and last stages provide D-type Serial Data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode Select and data inputs on the74F194 are edge-triggered, responding only to the Low-to-High transition of the Clock (CP). Therefore, the only timing restriction is that the Mode Select and selected data inputs must be stable one setup time prior to the Low-to-High transition of the clock pulse. Signals on the Mode Select, Parallel Data (D0–D3) and Serial Data(DSR, DSL) can change when the clock is in either state, provide donly the recommended setup and hold times, with respect to the clock rising edge, are observed. The four Parallel Data inputs(D0–D3) are D-type inputs. Data appearing on (D0–D3) inputs whenS0 and S1 are High is transferred to the Q0–Q3 outputs respectively, following the next Low-to-High transition of the clock. When Low, the asynchronous Master Reset (MR) overrides all other input conditions and forces the Q outputs Low

Features :-

• Shift right and shift left capability
• Synchronous parallel and serial data transfer
• Easily expanded for both serial and parallel operation
• Asynchronous Master Reset
• Hold (do nothing) mode

The 74HC194/74HCT194 is a 4-bit bidirectional universal shift register. The synchronous operation of the device is determined by the mode select inputs (S0, S1). In parallel load mode (S0 and S1 HIGH) data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs. When S0 is HIGH and S1 is LOW data is entered serially via DSL and shifted from left to right; when S0 is LOW and S1 is HIGH data is entered serially via DSR and shifted from right to left. DSR and DSL allow multistage shift right or shift left data transfers without interfering with parallel load operation. If both S0 and S1 are LOW, existing data is retained in a hold mode. Mode select and data inputs are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. When LOW, the asynchronous master reset (MR) overrides all other input conditions and forces the Q outputs LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.