74LS573 3-State Octal D-Type Latch IC (74573) DIP-20 Package

The 74F533 consists of eight latches with 3-STATE outputs for   bus   organized   system   applications.   The   flip-flops appear transparent to the data when Latch Enable (LE) is HIGH.  When  LE  is  LOW,  the  data  that  meets  the  setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.

Features :-

• Eight latches in a single package
• 3-STATE outputs for bus interfacing

The 74HC137 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The 74HC137 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS137. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features:-

• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent controls
• Active LOW mutually exclusive outputs
• Low-power dissipation
• Complies with JEDEC standard no. 7A
• Multiple package options

74HC158 is a 16 Pin Quad 2-Input Multiplexer IC having 2V to 6V Operating Voltage range with 1uA Low Input current and high noise immunity. It select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions.

Features:-

• Common Select Input
• Separate Enable Inputs
• Buffered inputs and Outputs
• Fanout (Over Temperature Range)
• Standard Outputs  : 10 LSTTL Loads
• Bus Driver Outputs : 15 LSTTL Loads
• Wide Operating Temperature Range : -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
• 2V to 6V Operation
• High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V
• HCT Types-
• 4.5V to 5.5V Operation
• Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)
• CMOS Input Compatibility, Il≤1μA at VOL, VOH

 

This 8-bit flip-flop features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs. A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The output enable (OE) does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74F574 is characterized for operation from 0°C to 70°C.

Features :-

• Eight D-Type Flip-Flops in a Single Package
• 3-State Bus-Driving True Outputs
• Full Parallel Access for Loading
• Buffered Control Inputs
• Package Options Include Plastic Small-Outline Packages and Standard Plastic 300-mil DIPs