74HC151 8-Input Multiplexer IC (74151 IC) DIP-16 Package

The 74F541 except that the inputs and outputs are on opposite sides of the package (see Connection Diagrams). This pinout arrangement makes these devices especially useful as output ports for microprocessors, allowing ease of layout and greater PC board density

Features :-

• 3-STATE outputs drive bus lines
• Inputs and outputs opposite side of package, allowing easier interface to microprocessors

The F74 is a dual D-type flip-flop with Direct Clear and Set inputs  and  complementary  (Q,  Q)  outputs.  Information  at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold  voltage  has  been  passed,  the  Data  input  is locked out and information present will not be transferred to the  outputs  until  the  next  rising  edge  of  the  Clock  Pulse input.

Features :-

• Asynchronous Inputs:
• LOW input to SD sets Q to HIGH level
• LOW input to CD sets Q to LOW level
• Clear and Set are independent of clock
• Simultaneous LOW on CD and SD makes both Q and Q HIGH

The 74F182 is a high-speed carry lookahead generator. It is  generally  used  with  the  74F181  or  74F381  4-bit  arithmetic  logic  units  to  provide  high-speed  lookahead  over word lengths of more than four bits

Features :-

• Provides lookahead carries across a group of four ALUs
• Multi-level  lookahead  high-speed  arithmetic  operation over long word lengths

74HC109 Dual J-K Positive-Edge-Triggered Flip-Flop IC – DIP-16 Package The 74HC109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product is known as 74109 IC, 74109 SMD IC, 74HC109 IC, 74HC109 SMD IC, Components, Dual J-K Positive-Edge-Triggered Flip-Flops IC, Dual J-K Positive-Edge-Triggered Flip-Flops SMD IC, SN74HC109D, CD74HC109M, 74HC109D, CD74HC109E, SN74HC109N, CD74HC109ME4.

Features :-

• Input Levels :

– For 74HC109: CMOS level – For 74HCT109: TTL level

• J and K inputs for easy D-type flip-flop
• Toggle flip-flop or “do nothing” mode
• Specified in compliance with JEDEC standard no. 7A
• ESD protection:

– HBM JESD22-A114F exceeds 2000 V – MM JESD22-A115-A exceeds 200 V

• Multiple package options