74LS51 Dual 2-Wide 2-Input AND/OR Inverter Gate IC (7451) DIP-14 Package

The 74F533 consists of eight latches with 3-STATE outputs for   bus   organized   system   applications.   The   flip-flops appear transparent to the data when Latch Enable (LE) is HIGH.  When  LE  is  LOW,  the  data  that  meets  the  setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.

Features :-

• Eight latches in a single package
• 3-STATE outputs for bus interfacing

The 74HC194/74HCT194 is a 4-bit bidirectional universal shift register. The synchronous operation of the device is determined by the mode select inputs (S0, S1). In parallel load mode (S0 and S1 HIGH) data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs. When S0 is HIGH and S1 is LOW data is entered serially via DSL and shifted from left to right; when S0 is LOW and S1 is HIGH data is entered serially via DSR and shifted from right to left. DSR and DSL allow multistage shift right or shift left data transfers without interfering with parallel load operation. If both S0 and S1 are LOW, existing data is retained in a hold mode. Mode select and data inputs are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. When LOW, the asynchronous master reset (MR) overrides all other input conditions and forces the Q outputs LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74F182 is a high-speed carry lookahead generator. It is  generally  used  with  the  74F181  or  74F381  4-bit  arithmetic  logic  units  to  provide  high-speed  lookahead  over word lengths of more than four bits

Features :-

• Provides lookahead carries across a group of four ALUs
• Multi-level  lookahead  high-speed  arithmetic  operation over long word lengths

This device contains gates configured to perform a 4-2-3-2input AND-OR-INVERT function.