74LS10 Triple 3-Input NAND Gate IC (7410 IC) DIP-14 Package

The 74HC137 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The 74HC137 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of decoders. The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally and pin equivalent to the 74LS137. All inputs are protected from damage due to static discharge by diodes to VCC and ground.

Features:-

• Combines 3-to-8 decoder with 3-bit latch
• Multiple input enable for easy expansion or independent controls
• Active LOW mutually exclusive outputs
• Low-power dissipation
• Complies with JEDEC standard no. 7A
• Multiple package options

The 74F138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active low outputs (Q0 – Q7). The device features three enable inputs; two active low (E0, E1) and one active high (E2). Every output will be high unless E0 and E1 are low and E2 is high. This multiple enable function allows easy parallel expansion of the device to 1–of–32 (5 lines to 32 lines) decoder with just four 74F138s and one inverter The device can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Enable inputs not used must be permanently tied to their appropriate active high or active low state.

Features :-

• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Industrial temperature range available (–40°C to +85°C)

 

The F74 is a dual D-type flip-flop with Direct Clear and Set inputs  and  complementary  (Q,  Q)  outputs.  Information  at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold  voltage  has  been  passed,  the  Data  input  is locked out and information present will not be transferred to the  outputs  until  the  next  rising  edge  of  the  Clock  Pulse input.

Features :-

• Asynchronous Inputs:
• LOW input to SD sets Q to HIGH level
• LOW input to CD sets Q to LOW level
• Clear and Set are independent of clock
• Simultaneous LOW on CD and SD makes both Q and Q HIGH

The 74F541 except that the inputs and outputs are on opposite sides of the package (see Connection Diagrams). This pinout arrangement makes these devices especially useful as output ports for microprocessors, allowing ease of layout and greater PC board density

Features :-

• 3-STATE outputs drive bus lines
• Inputs and outputs opposite side of package, allowing easier interface to microprocessors