74HC00 Quad 2-Input NAND Gate IC (7400 IC) DIP-14 Package

74HC109 Dual J-K Positive-Edge-Triggered Flip-Flop IC – DIP-16 Package The 74HC109 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product is known as 74109 IC, 74109 SMD IC, 74HC109 IC, 74HC109 SMD IC, Components, Dual J-K Positive-Edge-Triggered Flip-Flops IC, Dual J-K Positive-Edge-Triggered Flip-Flops SMD IC, SN74HC109D, CD74HC109M, 74HC109D, CD74HC109E, SN74HC109N, CD74HC109ME4.

Features :-

• Input Levels :

– For 74HC109: CMOS level – For 74HCT109: TTL level

• J and K inputs for easy D-type flip-flop
• Toggle flip-flop or “do nothing” mode
• Specified in compliance with JEDEC standard no. 7A
• ESD protection:

– HBM JESD22-A114F exceeds 2000 V – MM JESD22-A115-A exceeds 200 V

• Multiple package options

The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems.

The 74HC194/74HCT194 is a 4-bit bidirectional universal shift register. The synchronous operation of the device is determined by the mode select inputs (S0, S1). In parallel load mode (S0 and S1 HIGH) data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs. When S0 is HIGH and S1 is LOW data is entered serially via DSL and shifted from left to right; when S0 is LOW and S1 is HIGH data is entered serially via DSR and shifted from right to left. DSR and DSL allow multistage shift right or shift left data transfers without interfering with parallel load operation. If both S0 and S1 are LOW, existing data is retained in a hold mode. Mode select and data inputs are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. When LOW, the asynchronous master reset (MR) overrides all other input conditions and forces the Q outputs LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74F182 is a high-speed carry lookahead generator. It is  generally  used  with  the  74F181  or  74F381  4-bit  arithmetic  logic  units  to  provide  high-speed  lookahead  over word lengths of more than four bits

Features :-

• Provides lookahead carries across a group of four ALUs
• Multi-level  lookahead  high-speed  arithmetic  operation over long word lengths